Modern integrated circuits (ICs) contain millions of individual elements that are formed by patterning the materials, such as silicon, metal and/or dielectric layers. A set of processing steps is performed on a semiconductor wafer to from the circuit elements. For example, in lithography process, a process layer is formed on the semiconductor wafer, and a photoresist pattern then formed on the process layer by performing known photolithography techniques. In the fabrication of a semiconductor device, its patterns are fabricated in various planes. A semiconductor device is completed with a plurality of planes on which the individual patterns of the elements are located. The orientation of each plane with respect to one another is of considerable importance. If a plane was shifted too much with respect to a previous or subsequent plane, this could result in an interruption of the connection between the elements in one plane and the next.
In order to integrate increasing numbers of the circuit elements onto an IC, it has been necessarily to reduce the dimensions of the circuit elements; however, the critical dimensions (CDs) of the elements decrease accordingly. The CD refers to the smallest width of a connecting line or the smallest space between two lines permitted in the fabrication of a semiconductor device, which is used to monitor the pattern accuracy of the semiconductor device. Scaling-down the pitch of a gate in a semiconductor device decreases the space between features of the element, e.g., the gate electrode and the doped region of a transistor, and there might be no overlay window, which has a high risk of short circuits. The smaller the CD of a semiconductor device is, the less the CD variation is allowed. Moreover, as the dimension of the electronic device decreases, the complexity of processing and fabricating semiconductor devices is increased, and the probability of misalignment is also increased.
A self-aligned contact (SAC) process is developed to more reliably fabricate smaller semiconductor device structures at higher density. The SAC process includes forming an insulating layer covering an etched gate electrode. However, a high risk of short circuits occurs between the gate electrode and a contact pad induced by a metal residue due to CD variation.